VLSI Architecture of Pipelined Adaptive Edge-Enhanced Image Scalar for Image Processing Applications

In this paper, pipelining concepts is adopted to increase the processing speed of image scaling algorithms. The proposed algorithm consists of pipelining stages along with a linear space-variant edge detector, a low complicacy sharpening spatial filter, and a simplified bilinear interpolation. The linear space-edge detector is used to discover the image edges by a lowcost catching technique. The sharpening spatial filter serves as Pre filters in solving the blurring edges caused by the bilinear interpolation. An adaptive technology is used to enhance the edge contrast of image & improves the apparent sharpness effect of the edge detector by adaptively selecting the input pixels of the bilinear interpolation. Winscale method is used for the area pixel model. An algebraic manipulation and a hardware sharing techniques are used to simple the bilinear interpolation. Bilinear interpolation decreases the computing resources and silicon area in VLSI circuits. When compared with previous low complicacy techniques, this paper performs high speed, better quality, very good performance, less memory requirements, and a cheap hardware cost than other image scalar methods KEYWORDS—Sharpening spatial filter, Edge detector, Bilinear interpolation, Pipelining.